1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, for example, relates to a fabricating method by which an opening is formed in a low dielectric constant dielectric film.
2. Related Art
In recent years, with ever higher integration and higher performance of semiconductor integrated circuits (LSI), new microprocessing technologies have been developed. In particular, to achieve an ever faster speed of LSI, there has been a growing trend recently to replace the conventional wire material of aluminum (Al) alloys with copper (Cu) or Cu alloys (hereinafter, called Cu together) having lower resistance. Since it is difficult to apply the dry etching method, which is frequently used for forming an Al alloy wire, to Cu for microprocessing, the so-called damascene process is mainly adopted for Cu, in which a Cu film is deposited on a dielectric film to which groove processing has been provided and then the Cu film is removed except in portions where the Cu film is embedded inside a groove by chemical-mechanical polishing (CMP) to form an embedded wire. The Cu film is generally formed as a laminated film to a thickness of about several hundred nm by the electro-plating method after a thin seed layer being formed by the sputter process. Further, when a multilayer Cu wire is formed, a dielectric film is deposited on a lower layer wire and a predetermined via hole is formed to embed Cu to be a plug material, which is further connected to an upper layer wire.
Then recently, the use of a low dielectric constant material film (low-k film) having a low relative dielectric constant is examined as an inter-level dielectric. That is, an attempt is made to reduce parasitic capacitance between wires by using a low dielectric constant material film (low-k film) whose relative dielectric constant k is 2.6 or less, instead of a silicon oxide film (SiO2) whose relative dielectric constant k is about 4.2. Particularly, a process using a so-called porous dielectric film having minute holes in the dielectric film to make the dielectric constant lower has been developed. Then, when a Cu wire is formed by the above damascene process, a wire groove and a via hole need to be formed in the porous dielectric film by etching. At this point, a dielectric film of different film quality is formed on the under surface of the porous dielectric film as an etching stopper film to suppress the amount of etching. Normally, the etching stopper film has a higher relative dielectric constant than the porous dielectric film. Thus, a study of making the dielectric constant of the etching stopper film lower has been done to reduce capacitance between wires, but it is difficult to achieve both maintenance of film quality as an etching stopper and a lower dielectric constant. Thus, it is necessary to make the etching stopper film thinner to reduce capacitance between wires.
However, if the etching stopper film is made thinner, etching may not be stoppable by the etching stopper film in a wire or via plug shape process. This is because of a difference of the amount of etching due to a difference in pattern density. The etching stopper film may disappear for some patterns before a porous dielectric film is bored for all patterns so that the substrate, which is a base material, is unnecessarily etched. Thus, a problem of electric characteristics of wires in lower layers being adversely affected enormously is caused. If the etching stopper film is made thicker to avoid etching of the substrate, which is a base material, capacitance between wires increases, as described above, and if, on the other hand, the etching stopper film is made thinner, there is a possibility that the substrate, which is a base material, may also be etched. Thus, both making the etching stopper film thinner and thicker has respective problems, necessitating other process technology development to further reduce capacitance between wires.
Here, a technology to convert first and second spare porous dielectric layers into porous layers after forming the second spare porous dielectric layer containing a second porogen on the first spare porous dielectric layer containing a first porogen and etching a trench in the second spare porous dielectric layer and a via hole in the first spare porous dielectric layer is disclosed. A difference in etching between layers in this case should be realized by the use of porogen in each dielectric layer (for example, United States Patent Application Publication No. US2004/0130032). However, in this technology, only an interlayer etching difference between a layer in which a trench is formed and that in which a via hole is formed is described and suppression of an etching difference due to a difference in pattern density of patterns in one layer is not intended. Moreover, even if an attempt is made to apply the technology to patterns in one layer, a problem that two dielectric layers of different conditions must be laminated remains to be solved.